A SAT-Based Implication Engine

نویسندگان

  • Paul Tafertshofer
  • Andreas Ganz
  • Manfred Henftling
چکیده

This paper presents a flexible and efficient approach to evaluating implications as well as deriving indirect implications in logic circuits. Evaluation and derivation of implications are essential in ATPG, equivalence checking, and netlist optimization. Contrary to other methods, our approach is based on a graph model of a circuit’s clause description called the implication graph. It combines both the flexibility of SAT-based techniques and high efficiency of structure based methods. As the proposed algorithms operate only on the implication graph, they are independent of the chosen logic. Evaluation of implications and computation of indirect implications are performed by simple and efficient graph algorithms. Experimental results for various applications relying on implication demonstrate the efficiency of our approach.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

ATPG Using Fast Justification and Propagation on the Implication Graph

Automatic Test Pattern Generation (ATPG) primarily has to solve three fundamental Boolean problems: justification, propagation, and implication. In the past, various data structures (e.g. netlists, CNFs, decision diagrams) have been used to tackle these problems with none of them being specifically optimized for all these tasks. That is why we propose fast and optimized algorithms for justifica...

متن کامل

A Fast Heuristic Algorithm for Redundancy Removal

Redundancy identification is an important step of the design flow that typically follows logic synthesis and optimization. In addition to reducing circuit area, power consumption, and delay, redundancy removal also improves testability. All commercially available synthesis tools include a redundancy removal engine which is often run multiple times on the same netlist during optimization. This p...

متن کامل

Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction

Boolean satisfiability (SAT) is a core non polynomial (NP)-complete problem. Several heuristic software and hardware approaches have been proposed to solve this problem. The authors present a hardware solution to the SATproblem.They propose a custom integrated circuit (IC) to implement their approach, in which the traversal of the implication graph as well as conflict clause generation are perf...

متن کامل

Enhancing Sat-based Formal Verification Methods Using Global Learning

ABTRACT With the advances in VLSI and System-On-Chip (SOC) technology, the complexity of hardware systems has increased manifold. Today, 70% of the design cost is spent in verifying these intricate systems. The two most widely used formal methods for design verification are Equivalence Checking and Model Checking. Equivalence Checking requires that the implementation circuit should be exactly e...

متن کامل

Midisat -technical Report

Many DPLL-based [1] SAT solvers use an implementation of the two-literal watching scheme (TLWS) first used in Chaff [6] for boolean constraint propagation (BCP). For the extreme case of binary clauses this otherwise efficient algorithm has a large overhead in memory usage. In this report a technique called implication table for augmenting TLWS will be described and mathematically analyzed, that...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1997